The invention is related to a pulse coded time division multiplex (PCM) telecommunication system, especially a telephone system. More specifically, the invention is related to a circuit arrangement for compensating phase differences resulting from deviations between rates of an external clock pulse train controlling information transfer across an incoming transmission line and of a non-synchronous internal clock pulse train controlling switching operations of an exchange.
In particular for non-synchronous, especially plesiochronous operation of an external transmission line and the exchange system, such circuit arrangements comprise a small intermediate store which receives pieces of PCM information from the transmission line and a buffer memory connected by its input side to the intermediate store. The output side of the buffer memory is coupled to a switching network of the exchange. Buffering of incoming PCM information serves to compensate a phase difference caused by frequency deviations of the external and the internal clock pulse rates.
A known circuit arrangement of this type is described in German Auslegeschrift No. 2,641,488. There is provided an intermediate store for intercepting phase fluctuations of the external line clock pulse rate. The storage possesses a storage capacity corresponding to the likely maximum fluctuation range of the phase position of this external clock pulse rate. In a preferred embodiment, a storage capacity of 8 PCM words is implemented for balancing fluctuation of .+-.4 PCM words. During the operation of this intermediate store due to a frequency difference between the external line clock pulse rate and the internal exchange clock pulse rate, the theoretical off-set of four storage locations alternately selected for read operations and write operations can become lower. When such frequency difference is maintained for a plurality of cycles, write-in times and read-out times with respect to a specific storage location can move towards one another to such an extent that directly adjacent storage locations are affected by consecutive write-in and read-out operations.
If this state has arisen due to a higher external clock pulse rate of the exchange system, read-out operations from the intermediate store are effected at a frequency twice as high as normal in using a second bit-clock-pulse during the exchange system cycle for another read-out. On the contrary, if the internal clock pulse rate is higher, read-out is effected several times consecutively from one and the same storage location. Following to an extraordinary read-out of this kind from the intermediate store, the times of write-in and read-out operations with regard to one and the same storage location have been separated with sufficient extent to avoid overlapping.
Evidently, the control of this extraordinary read-out operation is somewhat complicated. Positive or negative frequency differences have to be evaluated. Additionally, starting time and duration of the extraordinary operation have to be taken into account. All these measures require a relatively large control outlay.
Therefore, it is an object of the present invention to provide an improved circuit arrangement for compensating phase differences with respect to processing PCM information in such a plesiochronous telecommunication system.